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   得獎經歷 / 專利 向國瑜 Kuo-Yu Hsiang 國立陽明交通大學 電子研究所 獲獎摘要 博士研究生  向國瑜同學於國立陽明交通大學電子研究所攻讀博士班,研究領域為鐵電與反鐵電記憶體之可靠度 測試及改善方案設計開發。迄今,相關研究成果包含以第一作者發表 IEEE 國際頂尖會議論文 IEDM 與 Symposium on VLSI Technology 各一篇、IEEE 國際重要可靠性會議論文 IRPS 2 篇、頂級國際 期刊論文 IEEE EDL 2 篇與 IEEE TED 3 篇,且榮獲 2022 IEDM Top Ranked Student Paper 受邀投 稿 IEEE T-ED,同時也作為第一發明人提出 4 項美國專利申請中。另與台積電、陽明交大、臺大實 驗室合作期間共同發表 6 篇 IEDM / Symposium on VLSI Technology。   • 2022~2024以第一發明人申請三項美國專利中 • 2022 Top Ranked Student Paper of IEDM 受邀投稿 2023 IEEE T-ED Special Issue • 2021 以第一發明人申請美國專利 US17848806-Integrated circuit device and method for fabricating the same • 2020科技部培育優秀博士生獎學金 重要學術著作 1. K.-Y. Hsiang et al., "Novel Opposite Polarity Cycling Recovery (OPCR) of HfZrO2 Antiferroelectric-RAM with an Access Scheme Toward Unlimited Endurance," in IEEE International Electron Devices Meeting (IEDM), 2022, pp. 32.5.1-32.5.4. 2. K.-Y. Hsiang et al., "FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations," in Symposium on VLSI Technology, 2023, T2-4. 3. K.-Y. Hsiang et al., "Dielectric Layer Design of Bilayer Ferroelectric and Antiferroelectric Tunneling Junctions Toward 3D NAND-Compatible Architecture," IEEE Electron Device Letters, vol. 43, no. 11, pp. 1850-1853, 2022. 4. K.-Y. Hsiang et al., "Bilayer-Based Antiferroelectric HfZrO2 Tunneling Junction with High Tunneling Electroresistance and Multilevel Nonvolatile Memory," IEEE Electron Device Letters, vol. 42, no. 10, pp. 1464-1467, 2021. 5. K.-Y. Hsiang et al., "Unleashing Endurance Limits of Emerging Memory: Multi-Level FeRAM Recovery Array Empowered by a Coordinated Inverting Amplifier Circuit," IEEE Transactions on Electron Devices, vol. 71, no. 4, pp. 2708-2713, 2024. 6. (Invited) K.-Y. Hsiang et al., "Fatigue Mechanism of Antiferroelectric Hf0.1Zr0.9O2 Toward Endurance Immunity by Opposite Polarity Cycling Recovery (OPCR) for eDRAM," IEEE Transactions on Electron Devices, vol. 70, no. 4, pp. 2142-2146, 2023. 7. K.-Y. Hsiang et al., "Ferroelectric HfZrO2 with Electrode Engineering and Stimulation Schemes as Symmetric Analog Synaptic Weight Element for Deep Neural Network Training," IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4201-4207, 2020. 8. Y.-C. Chen, K.-Y. Hsiang et al., "Monte-Carlo Modeling and Characterization of Switching Dynamics for Antiferroelectric/Ferroelectric HZO considering Mechanisms of Fatigue," in IEEE International Electron Devices Meeting (IEDM), 2022, pp. 13.4.1-13.4.4. 9. C.-Y. Liao, K.-Y. Hsiang et al., "Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM," in Symposium on VLSI Technology, 2022, pp. 393-394. 10.Y.-C. Chen, K.-Y. Hsiang et al., "NLS based Modeling and Characterization of Switching Dynamics for Antiferroelectric/Ferroelectric Hafnium Zirconium Oxides," in IEEE International Electron Devices Meeting (IEDM), 2021, pp. 15.4.1-15.4.4.   指導教授 侯拓宏 講座教授 現職 ・ 國立陽明交通大學 / 電子研究所 學歷 ・ 美國康乃爾大學 / 電機工程博士 經歷 ・ 台灣半導體研究中心 / 主任    ・ 科技部 A 世代半導體專案計畫 / 召集人    ・ IEEE 台北分會 / 理事    ・ 台灣電子材料與元件協會 / 常務理事 李敏鴻 教授 現職 ・ 國立臺灣大學 / 重點科技研究學院 學歷 ・ 國立臺灣大學 / 電機工程博士 經歷 ・ 國立臺灣師範大學 / 優聘教授 (2017~2019) (2022~2023)    ・ 國立臺灣師範大學 / 光電所所長 (2014~2017)    ・ IEEE Senior Member Taiwan Semiconductor Industry Association ┃台灣半導體產業協會 53   理事長的話 議程與講員簡歷 歷屆理事長重要事蹟與貢獻 TSIA 半導體獎 專題報導 活動報導 附錄 


































































































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