Page 64 - TSIA 2024 年會_年刊

62 2024 得獎經歷 / 專利 • 2022 / 2023 未來科技獎 • 2022 SNDCT 學生論文競賽特優獎、2023 SNDCT 學生論文競賽佳作獎 • 2022臺大1975級電機系系友科技研究創新獎 • 2021 / 2023 臺大電子所學生傑出研究獎 重要學術著作 • 2019~2022 國立臺灣大學優秀博士生獎學金 • 2019~2022 台積電 - 臺灣大學聯合研發中心獎助學金 • 台積電2020年博士獎學金 • 以第一發明人申請 1 項美國專利，以共同發明人申請 2 項美國專利 劉亦浚 Yi-Chun Liu 國立臺灣大學 電子工程學研究所 獲獎摘要 博士研究生 劉亦浚同學於國立臺灣大學電子工程學研究所攻讀博士班，研究領域為高效能之高層數堆疊鍺 矽奈米線及奈米片電晶體，並成功整合極高介電係數閘極堆疊，進一步提升電晶體驅動電流。 相 關 研 究 成 果 發 表 於 IEEE 頂 尖 國 際 會 議 Symposium on VLSI Technology 和 一 流 之 Nature: Communications Engineering、IEEE TED 等國際期刊。成果豐碩，難能可貴。 1. Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Hsin-Cheng Lin, Wan-Hsuan Hsieh, Chien-Te Tu, Bo-Wei Huang, Wei-Jen Chen, Chun-Yi Cheng, Shee-Jier Chueh, and C. W. Liu, "Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record ION per Footprint of 9200μA/ μm and Record ION per Stack of 360μA at VOV=VDS=0.5V," Symposium on VLSI Technology and Circuits (VLSI), 2023. 2. Yu-Rui Chen, Yi-Chun Liu, Hsin-Cheng Lin, Chien-Te Tu, Tao Chou, Bo-Wei Huang, Wan-Hsuan Hsieh, Shee-Jier Chueh, and C. W. Liu, "Fabrication and performance of highly stacked GeSi nanowire field effect transistors," Communications Engineering, 2, 77, pp. 1-9, 2023. 3. Wei-Jen Chen, Yi-Chun Liu, Yun-Wen Chen, Yu-Rui Chen, Hsin-Cheng Lin, Chien-Te Tu, Bo-Wei Huang, and C. W. Liu, "Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into 8 Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION," IEEE Transactions of Electron Devices, vol. 70, no. 12, pp. 6673-6679, 2023. 4. Yi-Chun Liu, Chien-Te Tu, Chung-En Tsai, Yu-Rui Chen, Jyun-Yan Chen, Sun-Rong Jan, Bo-Wei Huang, Shee-Jier Chueh, Chia-Jung Tsen, and C. W. Liu, "First Highly Stacked Ge0.95Si0.05 nGAAFETs with Record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and High Gm,max = 340 μS (13000 μS/μm) at VDS=0.5V by Wet Etching," Symposia on VLSI Technology and Circuits (VLSI), 2021. 5. Yi-Chun Liu, Chien-Te Tu, Chung-En Tsai, Bo-Wei Huang, Chun-Yi Cheng, Shee-Jier Chueh, Jyun-Yan Chen, and C. W. Liu, "Highly Stacked GeSi Nanosheets and Nanowires by Low-Temperature Epitaxy and Wet Etching," IEEE Transactions on Electron Devices, Vol. 68, No. 12, pp. 6599-6604, Dec. 2021. 6. Chung-En Tsai, Yi-Chun Liu, Chien-Te Tu, Bo-Wei Huang, Sun-Rong Jan, Yu-Rui Chen, Jyun-Yan Chen, Shee-Jier Chueh, Chun-Yi Cheng, Chia-Jung Tsen, Yichen Ma, and C. W. Liu, "Highly Stacked 8 Ge0.9Sn0.1 Nanosheet pFETs with Ultrathin Bodies (~3nm) and Thick Bodies (~30nm) Featuring the Respective Record ION/IOFF of 1.4x107 and Record ION of 92μA at VOV=VDS= -0.5V by CVD Epitaxy and Dry Etching," pp. 569-572, International Electron Devices Meeting (IEDM), 2021. 7. Yi-Chun Liu, Yu-Shiang Huang, Fang-Liang Lu, Hung-Yu Ye, Chien-Te Tu, and C. W. Liu, "Novel vertically stacked Ge0.85Si0.15 nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhanced ION (1.7X at VOV = VDS = 0.5 V) by Ge0.85Si0.15 channels," Semicond. Sci. Technol., Vol. 35, No. 5, pp. 055010, Mar. 2020. 8. Chien-Te Tu, Yi-Chun Liu, Bo-Wei Huang, Yu-Rui Chen, Wan-Hsuan Hsieh, Chung-En Tsai, Shee-Jier Chueh, Chun-Yi Cheng, Yichen Ma, and C. W. Liu, "First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation," International Electron Devices Meeting (IEDM), 2022. 9. Yi-Chun Liu, Yu-Rui Chen, Yun-Wen Chen, Wei-Jen Chen, Chien-Te Tu, and C. W. Liu, "High-κ (47) Hf0.2Zr0.8O2 Gate Stacks Integrated into 8 Stacked Ge0.95Si0.05 Nanowire and Nanosheet nFETs to Significantly Enhance ION," 54th IEEE Semiconductor Interface Specialists Conference (SISC), 2023. 10. Yi-Chun Liu, Chun-Yi Cheng, Wan-Hsuan Hsieh, Bo-Wei Huang, Chien-Te Tu, and C. W. Liu, "Highly Stacked Ge0.95Si0.05 Nanowire nFETs Featuring High ION=140μA (6500μA/μm) at VOV=VDS=0.5V by Low Temperature Epitaxy and Wet Etching," 53rd IEEE Semiconductor Interface Specialists Conference (SISC), 2022. 指導教授 劉致為 教授 現職 ・ Distinguished / Chair Professor, National Taiwan University 學歷 ・ Ph.D. 1994 Electrical Engineering, Princeton University ・ M.S. 1987 and B.S. 1985, National Taiwan University 經歷 ・ IEEE Fellow (2018~) ・ Deputy General Director ( 副主任 , 2008~2013) / Senior full researcher ( 資深研究員 , 2011~), National Nano Device Labs ・ Research Director / Senior full researcher ( 資深研究員 ), ERSO / ITRI (2002~2005)