Page 62 - TSIA 2024 年會_年刊

2024 陳彥龍 Yen-Lung Chen 國立臺灣大學 電子工程學研究所 獲獎摘要 博士研究生 陳彥龍同學在博士班期間致力於次世代基因定序資料分析平台開發，修業期間開發一次世代定序基 因資料處理之端至端 (end-to-end) 加速晶片，該晶片能在平均 30 分鐘內完成從短序列回貼到基因 型查找之所有分析，達到與現有商用平台之千倍的能源效率，並且提供具有競爭力的精準度與敏感 度。另外該作品的前身，完整整合基因變異偵測之系統晶片，可以將原本需要 3 天以上的處理時間 縮短至 40 分鐘內，同時維持 99.6% 的精準度，以及一萬倍以上的能源效率。 60 得獎經歷 / 專利 • ISSCC 2020 Takuo Sugano Award for Outstanding Far-East Paper • Golden Medal, Macronix Golden Silicon Competition, 2020 • Outstanding Chip Design Award, National Chip Implementation Center, 2020 • 2nd Place, National IC Design Contest Award, Ministry of Education, Taiwan, 2020 重要學術著作 • Best Master Thesis Award, Taiwan Engineering Medicine Biology Association, 2019 • Master Thesis Award, IEEE Taipei Section, 2019 • 3rd Place, National IC Design Contest Award, Ministry of Education, Taiwan, 2019 1. Y.-L.Chen,C.-H.Yang,Y.-C.Wu,C.-H.Lee,W.-C.Chen,L.-Y.Lin,N.-S.Chang,C.-P.Lin,C.-S.Chen,J.-H.Hung,C.-H.Yang,"AFullyIntegrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing," IEEE International Solid-State Circuits Conference (ISSCC), pp. 44-45, Feb. 2023. 2. C.-H.Yang,Y.-C.Wu,Y.-L.Chen,C.-H.Lee,J.-H.Hung,C.-H.Yang,"A75.6MBase-pairs/sFPGAAcceleratorforFM-indexBasedPaired-end Short-Read Mapping," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022. 3. Y.-L. Chen, B.-Y. Chang, C.-H. Yang, T.-D. Chiueh, "A High-throughput FPGA Accelerator for Short-read Mapping of the Whole Human Genome," Transactions on Parallel and Distributed Systems (TPDS), vol. 32, no. 6, pp. 1465-1478, Jan. 2021. 4. Y.-C.Wu,Y.-L.Chen,C.-H.Yang,C.-H.Lee,C.-Y.Yu,N.-S.Chang,L.-C.Chen,J.-R.Chang,C.-P.Lin,H.-L.Chen,C.-S.Chen,J.-H.Hung,C.-H. Yang, "A 975mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28nm for Next-Generation Sequencing," IEEE Journal of Solid- State Circuit (JSSC) ISSCC Special Issue, vol. 55, no. 1, pp. 123-135, Jan. 2021. (*equally-credited authors) 5. P.-S.Huang,Y.-L.Chen,Y.-C.Lee,Z.-S.Fu,C.-H.Yang,"A28.8mWAcceleratorICforDarkChannelPriorBasedBlindImageDeblurring,"IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021. 6. Y.-C.Wu*,Y.-L.Chen*,C.-H.Yang,C.-H.Lee,C.-Y.Yu,N.-S.Chang,L.-C.Chen,J.-R.Chang,C.-P.Lin,H.-L.Chen,C.-S.Chen,J.-H.Hung,C.-H. Yang, "A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing," IEEE International Solid-State Circuits Conference (ISSCC) (highlighted paper), pp. 322-324, Feb. 2020. (*equally-credited authors) 7. Y.-C.Wu*,Y.-L.Chen*,C.-H.Yang,C.-H.Lee,C.-Y.Yu,N.-S.Chang,L.-C.Chen,J.-R.Chang,C.-P.Lin,H.-L.Chen,C.-S.Chen,J.-H.Hung,C.-H. Yang, "A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing," Hot Chips, 2020. (*equally-credited authors) 8. C.-H.Yang,Y.-C.Wu,Y.-L.Chen,J.-H.Hung,C.-H.Yang,"AnFM-indexBasedHigh-ThroughputMemory-EfficientFPGAAcceleratorforShort- Read Mapping," Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 17, no. 6, pp. 1331-1341, July 2023. 指導教授 楊家驤 教授 現職 ・Professor, Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University 學歷 ・Ph.D. (2010) in Electrical Engineering, University of California at Los Angeles ・M.S. (2004) and B.S. (2002) in Electrical Engineering, National Taiwan University 經歷 ・ TPC Member, International Solid-State Circuits Conference (ISSCC) ・ TPC Member, Symposium on VLSI Circuits (VLSI Circuits) ・ TPC Member, Asian Solid-State Circuit Conference (A-SSCC) ・ Senior Associate Editor, IEEE Signal Processing Letters (SPL) ・ Guest Editor, IEEE Journal of Solid-State Circuits (JSSC)