Page 65 - TSIA 2024 年會_年刊

蘇建維 Jian-Wei Su 國立清華大學 電機工程學系 獲獎摘要 博士研究生 蘇建維同學是國立清華大學電機工程學系的博士生，其研究專注於人工智慧中的記憶體內運算電 路。他的主要研究方向包括靜態隨機存取記憶體內運算電路的設計。在過去五年中，他的研究成 果連續發表於 IEEE 國際固態電路研討會 (ISSCC) 及國際固態電路期刊 (JSSC)，分別為 2020 年至 2024 年。此外，他也積極參與其他記憶體相關項目，包括電阻式記憶體、磁性記憶體和鐵電記憶 體的研究。 得獎經歷 / 專利 • 2024榮獲救國團新竹團委會「社會優秀青年」 • 2020~2023連續四年榮獲工研院頒發「年度論文獎」的肯定 • 2020~2021榮獲旺宏金矽獎「優勝獎」 • 2020~2024 已獲證發明專利 : 8 件(美國)，6 件(台灣)，1 件(日本) 重要學術著作 1. W.-S. Khwa, P.-C. Wu, J.-J. Wu, J.-W. Su et al., "34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 568-570. 2. P.-C. Wu, J.-W. Su (1st Co-author) et al., "A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips," in IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 1, pp. 196-207, Jan. 2024. 3. P.-C. Wu, J.-W. Su (1st Co-author) et al., "A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 126-128. 4. J.-W. Su (1st author) et al., "8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips," in IEEE Transactions on Circuits and Systems II (TCASII): Express Briefs, vol. 71, no. 4, pp. 2304-2308, April 2024. 5. P.-C. Wu, J.-W. Su (1st Co-author) et al., "An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips," in IEEE Journal of Solid-State Circuits (JSSC). 6. P.-C. Wu, J.-W. Su (1st Co-author) et al., "A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3. 7. J.-W. Su (1st author) et al., "A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips," in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 3, pp. 877-892, March 2023. 8. J.-W. Su (1st author) et al., "16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 250-252. 9. J.-W. Su (1st author) et al., "Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips," in IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 2, pp. 609-624, Feb. 2022. 10.J.-W. Su (1st author) et al., "15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 240-242. 指導教授 張孟凡 教授 現職 ・ 國立清華大學 / 電機工程學系特聘教授 ・ 台灣積體電路製造公司 (TSMC) Director of Corporate Research 學歷 ・ 國立陽明交通大學 / 電子工程博士 經歷 ・ IEEE Fellow (2019) ・台灣積體電路製造公司 (TSMC) Director of Corporate Research (2020~) ・International Solid-State Circuit Conference (ISSCC), Chair of Memory sub-committee (2021~) ・International Electron Devices Meeting (IEDM), Executive Committee (2018~) ・IEEE Taipei Section Chair (2019/1~2021/1) ・科技部 Program Director, Micro-Electronics Engineering Program (2018/1~2020/12) ・國立清華大學 / 電機工程學系特聘教授 (2019/8~) ・國立清華大學 / 電機工程學系教授 (2014/8) ・國立清華大學 / 電機工程學系副教授 (2006/8) Taiwan Semiconductor Industry Association ┃台灣半導體產業協會 63 理事長的話 議程與講員簡歷 歷屆理事長重要事蹟與貢獻 TSIA 半導體獎 專題報導 活動報導 附錄